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695 mhz to 2700 mhz, quadrature demodulator with integrated fractional - n pll and vco data sheet ADRF6820 features i/q d em odulator with i ntegrated fractional - n pll rf input frequency range: 695 mhz to 2700 mhz internal lo frequency range: 356.25 mhz to 2850 mhz input p1db: 14.5 dbm at 1900 mhz rf input ip3: 37 dbm at 1900 mhz rf programmable hd3/ip3 trim single pole, double throw ( s pd t ) rf input switch rf digital step attenuat i o n range : 0 db to 15 db inte grated rf tunable balun for single - ended 50 input mult i core integrated vco demodulated 1 db bandwidth : 6 00 mhz 4 selectable baseband gain and ban dwidth modes digital programmable lo p hase offset and dc nulling programmable via 3 - wire serial port interface (spi) 40 - lead , 6 mm 6 mm lfcsp applications cellular w - cdma/gsm/lte digital predistortion (dpd) receivers microwave point - to - point radios functional block dia gram figure 1. general description the ADRF6820 is a highly integrated demodulator and synthesizer ideally suited for next generation communication systems. the feature rich device consists of a hi gh linearity broadband i / q demodulator, an integrated fractional - n phase - locked loop (pll), and a low phase noise multicore , voltage controlled oscillator (vco). t he ADRF6820 also integrates a 2:1 rf switch , an on - chip tunable rf balun, a programmable rf attenuator, and two low dropout ( ldo ) regulator s . this highly integrated device fits within a small 6 mm 6 mm footprint. the high isolation 2:1 rf switch and on - chip tunabl e rf balun enable the ADRF6820 to support two single - ended , 50 ? terminated rf inputs. a programmable attenuator ensures an optimal differential rf input level to the high linearity demodulato r core. the integrated attenuator offers an attenuation range of 0 db to 15 db with a step size of 1 db. the ADRF6820 offers two alternatives for generating the differential local oscillator (lo) input signal: externally via a high frequency , low phase noise lo signal or internally via the on - chip f ractional - n synthesizer. the integrated synthesizer enables continuous lo coverage from 356.25 mhz to 2850 mhz. the pll reference input can support a wide frequency range because the divide or multiplication blocks can increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (pfd). when selected, t he output of the internal f ractional - n s ynthesizer is applied to a d ivide - by - 2 quadrature phase splitter. from the external lo path, a 1 lo signal can be applied to the built - in polyphase filter , or a 2 lo signal can be used with the d ivide - by - 2 quadrature phase splitter to generate the quadra ture lo inputs to the mixers. the ADRF6820 is fabricated using an advanced silicon - germanium bicmos process. it is available in a 40 - lead , rohs - compliant, 6 mm 6 mm lfcsp package with an exposed paddle. performance is specified over the ? 40c to +85c temperature range. dc/phase correction dc/phase correction cs sclk sdio seria l port inter f ace 15 14 13 2 3 8 9 23 25 26 28 38 vpos_3p3 decl1 t o decl4 21 11 19 30 36 31 27 33 40 10 1 vpos_5v ldo vco ldo 2.5v rfin0 rfin1 29 22 po l yphase fi l ter loin? refin loin+ i+ i? q? q+ quad divider pl l 34 39 35 5 4 7 6 1 1990-001 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsi bility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under an y patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com
ADRF6820 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 system specifications ................................................................... 3 dynamic performance ................................................................. 3 synthesizer/pll specifications ................................................... 5 digital logic specifications ......................................................... 6 absolute maximum ratings ............................................................ 7 ther mal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 14 rf input switch .......................................................................... 14 tunable balun ............................................................................. 14 rf attenuator ............................................................................. 15 lo generation block ................................................................. 15 active m ixers .............................................................................. 17 baseband buffers ........................................................................ 17 serial port interface (spi) ......................................................... 17 applications information .............................................................. 18 basic connections ...................................................................... 18 rf balun i nsertion loss optimization ................................... 20 bandwidth select modes ........................................................... 22 ip3 and noise figure optimization ......................................... 24 i/q output loading ................................................................... 26 image reje ction .......................................................................... 27 i/q polarity .................................................................................. 28 layout .......................................................................................... 29 register map ................................................................................... 30 register address descriptions .................................................. 31 outline dimensions ....................................................................... 4 4 ordering guide .......................................................................... 44 revision history 1 2 /13 revision 0: initial version rev. 0 | page 2 of 44
data sheet ADRF6820 specifications system specification s vpos_5v = 5 v, vpos_3p3 = 3.3 v, ambient temperature (t a ) = 25c, high - side lo injection, internal lo mode, rf attenuation range = 0 db, input ip2/input ip3 tone spacing = 5 mhz and ?5 dbm per tone, f if = 40 mhz for bwsel = 0 and f if = 200 mhz for bwsel = 2. table 1 . parameter test conditions/comments min typ max unit rf input mhz rf frequency range 695 2700 mhz return loss 15 db input impedance 50 input power 18 dbm lo internal frequency mhz lo internal frequency range 356.25 2850 mhz external lo frequency range 350 6000 mhz lo input level ?6 +6 dbm lo input impedance 50 supply voltage v vpos_3p3 3.1 3.3 3.5 v vpos_5v 4.7 5.0 5.25 v rf attenuation range step size = 1 db 0 15 db if outputs gain flatness across any 20 mhz bandwidth 0.2 db quadrature phase error no correction applied 1 degrees i/q amplitude imbalance no correction applied 0.1 db output dc offset no correction applied 2 0 mv output common mode 1.5 2.4 v i/q output impedance differential 50 total power consumption external lo, polyphase filter lo path 1100 mw internal pll/vco, 2 lo path 1400 mw dynamic performance table 2 . bwsel0 1 bwsel2 1 parameter test conditions/comments min typ max min typ max unit demodulation bandwidth 1 db bandwidth, f lo = 2100 mhz 240 600 mhz 3 db bandwidth, f lo = 2100 mhz 480 1400 mhz f rf = 900 mhz conversion gain voltage gain +3.5 ?2.5 db input p1db 11 14 dbm input ip3 33 37 dbm input ip2 75 72 dbm noise figure internal lo 17 19 db external lo 16 18.5 db lo to rf leakage ?82 ?82 dbm rf to lo leakage ?67 ?67 dbm lo to if leakage with respect to ?5 dbm rf input power ?78.5 ?78.5 dbc rf to if leakage with respect to ?5 dbm rf input power ?49 ?49 dbc isolation 2 isolation between rfin0 to rfin1 ?55 ?55 dbc isolation between rfin1 to rfin0 ?55 ?55 dbc rev. 0 | page 3 of 44
ADRF6820 data sheet bwsel0 1 bwsel2 1 parameter test conditions/comments min typ max min typ max unit f rf = 1900 mhz conversion gain voltage gain +3 ?3 db input p1db 12 14.5 dbm input ip3 37 37 dbm input ip2 72 68 dbm noise figure internal lo 18 20 db external lo 17.5 19.5 db lo to rf leakage ?75 ?75 dbm rf to lo leakage ?64 ?64 dbm lo to if leakage with respect to ?5 dbm rf input power ?64.5 ?64.5 dbc rf to if leakage with respect to ?5 dbm rf input power ?43.5 ?43.5 dbc isolation 2 isolation between rfin0 to rfin1 ?51 ?51 dbc isolation between rfin1 to rfin0 ?39 ?39 dbc f rf = 2100 mhz conversion gain voltage gain +2.5 ?3 db input p1db 12 15.5 dbm input ip3 36 37 dbm input ip2 71 70 dbm noise figure internal lo 18 20.5 db external lo 18 20 db lo to rf leakage ?72.5 ?72.5 dbm rf to lo leakage ?62 ?62 dbm lo to if leakage with respect to ?5 dbm rf input power ?71 ?71 dbc rf to if leakage with respect to ?5 dbm rf input power ?45 ?45 dbc isolation 2 isolation bet ween rfin0 to rfin1 ?48.5 ?48.5 dbc isolation between rfin1 to rfin0 ?36.5 ?36.5 dbc f rf = 2650 mhz conversion gain voltage gain +1.5 ?4 db input p1db 13 16.5 dbm input ip3 36 36 dbm input ip2 71 68 dbm noise figure internal lo 19.5 22 db external lo 19.5 21.5 db lo to rf leakage ?70 ?70 dbm rf to lo leakage ?57 ?57 dbm lo to if leakage with respect to ?5 dbm rf input power ?76 ?76 dbc rf to if leakage with respect to ?5 dbm rf input power ?46 ?46 dbc isolation 2 isolation between rfin0 to rfin1 ?40.5 ?40.5 dbc isolation between rfin1 to rfin0 ?33 ?33 dbc 1 see table 15. 2 this is the isolation between the rf inputs. an input signal was applied to rfin0, while rfin1 was terminated with 50 . the if signal amplitude was measured at the baseband output. next, the internal switch was configured for rfin1, and the feedthrough was measured as a delta from the fundamental. this differen ce is recorded as isolation between rfin0 and rfin1. rev. 0 | page 4 of 44
data sheet ADRF6820 synthesizer/pll spec ifications vpos_5v = 5 v, vpos_3p3 = 3.3 v, ambient temperature (t a ) = 25c, f ref = 153.6 mhz, f ref power = 4 dbm, f pfd = 38.4 mhz, loop filter bandwidth = 20 khz, measured at lo output, table 3 . parameter test conditions/comments min typ max unit pll reference frequency 12 320 mhz amplitude 4 14 dbm pfd frequency 24 40 mhz internal vco range 2850 5700 mhz reference spurs f ref = 153.6 mhz, f pfd = 38.4 mhz, f lo = 1809.6 mhz f pfd /4 ADRF6820 data sheet digital logic specif ications table 4 . parameter test conditions/comments min typ max unit input voltage high, v ih 1.4 v input voltage low, v il 0.70 v output voltage high, v oh i oh = ? 100 a 2.3 v output voltage low, v ol i ol = 100 a 0.2 v serial clock period t clk 38 ns setup time between data and rising e dge of sclk t ds 8 ns hold time between data and rising edge of sclk t dh 8 ns setup time between falling edge of cs and sclk t s 10 ns hold time between rising edge of cs and sclk t h 10 ns minimum p eriod sclk in a logic high state t high 10 ns minimum p eriod sclk in a logic low state t lo w 10 ns maximum time delay between falling edge of sclk and output data valid for a read ope ration t a ccess 231 ns maximum time delay between cs d eactivation and sdio bus return to high impedance t z 5 ns timing diagram figure 2. setup and hold timing measurements t s t ds t dh t high t low t sclk t h don't care don't care a5 a4 a3 a2 a1 a0 d15 d14 d13 d3 d2 d1 d0 don't care don't care sclk sdio r/w t z t access a6 cs 1 1990-002 rev. 0 | page 6 of 44
data sheet ADRF6820 absolute maximum rat ings table 5 . parameter rating v pos _5v ? 0.5 v to + 5.5 v v pos _3p3 ? 0.3 v to + 3.6 v vocm ? 0.3 v to + 3.6 v cs , sclk, sd io ? 0.3 v to + 3.6 v rfsw ? 0.3 v to + 3.6 v rfin0, rfin1 2.5 v peak , ac - coupled enbl ? 0.3 v to + 3.6 v vtune ? 0.3 v to + 3.6 v loin ? , loi n + 16 dbm , differential refin ? 0.3 v to + 3.6 v operating temperature range ? 40 c to +85c storage temperature range ? 65c to + 150c maximum junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 6 . thermal resistance package type ja jc unit 40 -l ead lfcsp 31.93 1.12 c/w esd caution rev. 0 | page 7 of 44
ADRF6820 data sheet pin configuration an d function descripti ons figure 3. pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 , 19, 30, 31, 36 v pos _ 3p3 3.3 v power supp ly . 2, 3 , 8, 9, 23, 25, 26, 28, 38 gnd g round. 4, 5 i+, i ? differential baseband o utputs , i c hannel . 6, 7 q?, q+ differential baseband outputs , q c hannel . 10 decl 1 decoupl ing for mixer lo ad . connect a 0.22 f capacitor from decl1 to gnd . 11 , 21 v pos _5v 5 v power s upply. 12 vocm reference voltage input. this pin sets the output common - mode level. 13 sdio spi data . 14 sclk spi clock . 15 cs chip select, active low. 16 muxout mux output. output pin providing the pll reference signal or the pll lock detect . 17, 18 loout+ , lo out ? differential lo o utput s . 20 rfsw rf switch s elect . selects between rfin0 and rfin1 . 22 , 29 rfin1 , rfin0 rf i nput s . single pole , double throw switch input . 24 enbl enable , active high. 27 , 33 decl 2 , decl3 vco ldo d ecoupling . 32 vtune vco tuning voltage input. 34, 35 loin ? , loi n+ differential lo i nputs . 37 cp pll charge pump output. 39 refin pll reference i nput . 40 decl 4 2.5 v ldo d ecoupling . epad exposed pad. the exposed pad must be connected to a ground plane with low thermal impedance. notes 1. the exposed p ad must be connected t o a ground plane with low therma l impedance. t op view (not to scale) ADRF6820 p i n 1 i n d i c a t o r 1 vpos_3p3 30 vpos_3p3 40 gnd gnd i+ i? q? q+ gnd gnd decl1 2 3 4 5 6 7 8 9 10 rfin0 gnd decl2 gnd gnd enb l gnd rfin1 vpos_5v 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 decl3 loin? loin+ vpos_3p3 decl4 refin gnd cp vtune vpos_3p3 1 1 vpos_5v vocm sdio sclk cs muxout loout+ loout? vpos_3p3 rfsw 12 13 14 15 16 17 18 19 20 1 1990-003 rev. 0 | page 8 of 44
data sheet ADRF6820 typical performance characteristics vpos_5 v = 5 v, vpos_3p3 = 3.3 v, rfdsa_sel = 0, rfsw = 0 (rfin0), high - side lo , ?5 db per tone for two - tone measurement with 5 mhz tone spacing , unless otherwise noted. for bwsel0 , f if = 40 mhz , and for bwsel2 , f if = 200 mhz . fo r bal_cin, bal_cout, mix_bias, demo d_rdac, and demod_cdac , refer to table 16. figure 4 . voltage conversion gain vs. rf frequency over temperature figure 5 . input ip3 (iip3) and input ip2 (iip2) vs. lo frequency over temperature, bwsel = 0 figure 6 . noise figure vs. lo frequency, b wsel = 0 figure 7 . input p1db vs. lo frequency figure 8 . input ip3 (iip3) and input ip2 (iip2) vs. frequency over temperature, bwsel = 2 figure 9 . noise figure vs. lo frequency, bwsel = 2 ?8 ?6 ?4 ?2 0 2 4 6 640 1 140 1640 2140 2640 volt age conversion gain (db) rf frequenc y (mhz) bwse l = 0 bwse l = 2 t a = ?40c t a = +25c t a = +85c externa l lo interna l lo 1 1990-207 10 20 30 40 50 60 70 80 90 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700 2800 iip3 (dbm), iip2 (dbm) lo frequenc y (mhz) bwse l = 0 ?40c +25c +85c 1 1990-226 iip2 iip3 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 500 750 1000 1250 1500 1750 2000 2250 2500 2750 noise figure (db) lo frequenc y (mhz) externa l 2 lo nf externa l lo nf interna l lo nf 1 1990-222 t a = ?40c t a = +25c t a = +85c 640 1 140 1640 2140 2640 lo frequenc y (mhz) bwse l = 2 bwse l = 0 0 2 4 6 8 10 12 14 16 18 20 input p1db (dbm) t a = ?40c t a = +25c t a = +85c externa l lo interna l lo 1 1990-208 10 20 30 40 50 60 70 80 90 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700 2800 iip3 (dbm), iip2 (dbm) lo frequenc y (mhz) bwse l = 2 1 1990-227 iip2 iip3 ?40c +25c +85c 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 500 750 1000 1250 1500 1750 2000 2250 2500 2750 noise figure (db) lo frequenc y (mhz) 1 1990-204 t a = ?40c t a = +25c t a = +85c externa l 2 lo nf externa l lo nf interna l lo nf rev. 0 | page 9 of 44
ADRF6820 data sheet figure 10 . lo to rf feedthrough vs. lo frequency figure 11 . rf and lo feedthrough to if output, rf input ?5 dbm figure 12 . switch isolation vs. rf frequency figure 13 . i/q amplitude mismatch vs. lo frequency figure 14 . q uadrature phase mismatch vs. lo frequency ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 640 1 140 1640 2140 2640 lo t o rf feedthrough (dbm) lo frequenc y (mhz) lo_d r v_l vl = 1 1 lo_d r v_l vl = 00 lo driver disabled t a = ?40c t a = +25c t a = +85c externa l lo interna l lo 1 1990-210 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700 feedthrough (dbm) frequenc y (mhz) externa l lo interna l lo rf feedthrough 1 1990-223 lo feedthrough 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700 2800 isol a tion (dbc) rf frequenc y (mhz) rfin0 t o rfin1 rfin1 t o rfin0 1 1990- 1 10 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 640 890 1 140 1390 1640 1890 2140 2390 2640 i/q amplitude mism a tch (db) lo frequenc y (mhz) 1 1990-312 ?92 ?91 ?90 ?89 ?88 ?87 640 890 1 140 1390 1640 1890 2140 2390 2640 quadr a ture phase mism a tch (degrees) lo frequenc y (mhz) 1 1990-313 rev. 0 | page 10 of 44
data sheet ADRF6820 figure 15 . gain vs. common - mode voltage (v cm ) for f rf = 900 mhz, f rf = 1900 mhz, f rf = 2100 mhz, and f rf = 2650 mhz for bwsel = 0 and bwsel = 2 figure 16 . input p1db (ip1db) vs. common - mode voltage (v cm ) for f rf = 900 mhz, f rf = 1900 mhz, f rf = 2100 mhz, and f rf = 2650 mhz figure 17 . current consumption (i cc ) vs. common - mode voltage (v cm ), internal and external lo , f rf = 900 mhz, f rf = 1900 mhz, f rf = 2100 mhz, f rf = 2100 mhz, and f rf = 2650 mhz figure 18 . open - loop phase noise for 1 khz, 10 khz, 50 khz, 1 mhz, and 10 mhz offsets figure 19 . open - loop phase noise for 100 khz, 500 khz, 800 khz, and 40 mhz offsets figure 20 . close d - loop phase noise vs. lo frequency, 20 khz bandwidth loop filter , measured with div4_en = 1 (divide by 2) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 1.45 1.65 1.85 2.05 2.25 vo lt age convention gain (db) v cm (v) 900mhz 1900mhz 2100mhz 2650mhz bwse l = 0 bwse l = 2 1 1990-219 9 10 1 1 12 13 14 15 16 17 18 19 1.45 1.65 1.85 2.05 2.25 ip1db (dbm) v cm (v) 900mhz 1900mhz 2100mhz 2650mhz bwse l = 2 bwse l = 0 1 1990-220 0 50 100 150 200 250 300 350 1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25 i cc (ma) v cm (v) i cc (3.3v) , interna l lo i cc (3.3v) , externa l lo i cc (5v) 1 1990-221 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 2.85 3.35 3.85 4.35 4.85 5.35 phase noise (dbc/hz) vco frequenc y (ghz) 1khz offset 10khz offset 50khz offset 1mhz offset 10mhz offset t a = ?40c t a = +25c t a = +85c 1 1990-225 ?165 ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 2.85 3.35 3.85 4.35 4.85 5.35 phase noise (dbc/hz) vco frequenc y (ghz) 100khz offset 500khz offset 800khz offset 40mhz offset t a = ?40c t a = +25c t a = +85c 1 1990-224 ?160 ?155 ?150 ?145 ?140 ?135 ?130 ?125 ?120 ? 1 15 ? 1 10 ?105 ?100 ?95 ?90 1425 1550 1675 1800 1925 2050 2175 2300 2425 2550 2675 2800 phase noise (dbc/hz) lo frequenc y (mhz) 50khz offset 100khz offset 40mhz offset 500khz offset 200khz offset t a = ?40c t a = +25c t a = +85c 1mhz offset 1 1990-214 rev. 0 | page 11 of 44
ADRF6820 data sheet figure 21 . 1 pfd spurs vs. lo frequency, measured with div4_en = 1 (divide by 2) figure 22 . 2 pfd spurs vs. lo frequency, measured with div4_en = 1 (divide by 2) figure 23 . 3 pfd spurs vs. lo frequency, measured with div4_en = 1 (divide by 2) figure 24 . vpos_3p3 power supply current vs. lo frequency figure 25 . rfin0/rfin1 return loss for multiple bal_cin and bal_cout combinations figure 26 . return loss of unused rfinx port vs. frequency ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 reference spurs, 1 pfd (dbc) lo frequenc y (mhz) t a = ?40c t a = +25c t a = +85c 1 1990-2 1 1 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 reference spurs, 2 pfd (dbc) t a = ?40c t a = +25c t a = +85c 1 1990-212 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 lo frequenc y (mhz) ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 reference spurs, 3 pfd (dbc) lo frequenc y (ghz) t a = ?40c t a = +25c t a = +85c 1 1990-213 640 1 140 1640 2140 2640 lo frequenc y (mhz) 0 50 100 150 200 250 300 350 400 vpos_3p3 power supp l y current t a = ?40c t a = +25c t a = +85c externa l lo interna l lo 1 1990-209 ?30 ?25 ?20 ?15 ?10 ?5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 return loss (db) frequenc y (ghz) 1 1990-016 cin = 0, cout = 0 cin = 1, cout = 1 cin = 2, cout = 2 cin = 3, cout = 3 cin = 4, cout = 4 cin = 5, cout = 5 cin = 6, cout = 6 cin = 7, cout = 7 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 return loss (db) frequenc y (ghz) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 1990-035 rev. 0 | page 12 of 44
data sheet ADRF6820 figure 27 . lo input return loss vs. frequency figure 28 . lo output return loss vs. frequency figure 29 . i/q return loss vs. frequency ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 500 1500 2500 3500 4500 5500 return loss (db) frequenc y (mhz) 1 1990-036 ?30 ?25 ?20 ?15 ?10 ?5 0 500 1500 2500 3500 4500 5500 return loss (db) frequenc y (mhz) 1 1990-037 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 100 200 300 400 500 600 700 800 900 1000 return loss (db) frequenc y (mhz) 1 1990-038 rev. 0 | page 13 of 44
ADRF6820 data sheet theory of operation the ADRF6820 integrates many of the essential building blocks f or a high bandwidth quadrature demodulator and receiver, especially for the feedback downconverter path for the digital predistortion i n cellular base stations. the main features include a single pole , double throw (spdt) rf input switch, a variable rf attenuator , a tunable balun, a pair of active mixers, and two baseband buffers. additiona l l y , t he local oscillator (lo) signals for the mixers are generated by a fractional - n synthesizer and a multicore voltage controlled oscillator (vco) , covering an octave frequency range with low phase noise. a pair of flip - flops then divide s the lo frequency by two and generate s the in - phase and quadra ture phase l o signals to drive the mixers. the synthesizer uses a fractional - n phase - loop loop (pll) with additional frequency dividers to enable continuous lo coverage from 356.25 mhz to 2850 mhz. alternatively, a polyphase phase splitter is also availabl e to generate lo signals in quadrature from an external lo source. putting all the building blocks of the ADRF6820 together, the signal path through the device starts at one of two rf inputs selected by the input multi plexe r ( mux ) and is converted to a differential signal via a tunable balun. the differential rf signal is atten uated to an optimal input level via the digital step attenuator with 15 db of attenuation range in 1 db steps. the rf signal is then mixed with the lo signal in the gilbert cell mixers down to an intermediate frequency (if) or baseband. the emitter followers further buffer the outputs of the mixers with an adjustable output common - mode level. t he different sections of the ADRF6820 are controll ed through reg isters programmable via a serial port interface (spi). rf input switch the ADRF6820 integrates a spdt switch where one of two rf inputs is selected. selection of the desired rf input is achieve d externally via a control pin or serially via register writes to the spi. when compared to the serial write approach, pin con trol allows faster switching between the rf inputs. using the rfsw pin ( pin 20 ), the rf input can switch within 100 ns. when s erial port control is used, the switching time is dominated by the la tency of the spi programming, which is 2.4 s minimum for a 1 0 mhz serial clock. the rfsw_mux bit (register 0x23, bit 11) selects whether the rf input switch is controlled via the external pins or via the spi (see table 8 ) . by default at power - up, the device is configured for pin control. connecting rfsw to gnd selects rfin0 , and connecting rfsw to v pos _3p3 selects rfin1. in serial mode control, w riting to the rfsw_sel bit ( reg ister 0x23 , bit 9 ) allows selection of one of the two rf inputs . if only one rfin x port is used, the unused rf input must be p roperly terminate d to improve isolation. the rfin 0/ refin 1 ports are internally terminated with 50 ? resistors, a nd the dc level is at 2.5 v. to avoid disrupting the dc level, the recommended termination is a dc blocking capacitor to gnd. figure 30 shows the recommended configuration when o nly rfin0 is selected . figure 30 . terminating unused rf input ports tunable balun the ADRF6820 integrates a programmable balun operating over a 695 mhz to 2700 mhz frequency range . the tunable balun offers the benefit of ease of drivability with single - ended , 50 rf inputs , and the single - ended - to - differential conversion o f the integrated balun provides additional common - mode noise rejection. figure 31 . integrated tunable balun to accomplish rf balun tuning , switch the parallel capacitances on the primary and secondary sides of the balun by writing to register 0x30. the added capacitance in parallel with the inductive windings of the balun changes the res onant frequency of the inductor capacitor (lc) tank. therefore, sel ecting the proper combination of bal_cin (register 0x30, bits[3:1]) and bal_cout (register 0x30, bits[7:5]) sets the desired frequency and optimizes gain. under most circumstances, the input and output capacitance s are tuned together; however, sometimes fo r matching reasons, it is advantageous to tune them independently . table 8 . rf input selection table rfsw_mux (reg ister 0x23 , bit 11) rfsw_sel spi control (re g ister 0x23 , bit 9 ) rfsw pin control (pin 20) rf input 0 0 x 1 rfin0 0 1 x 1 rfin1 1 x 1 0 rfin0 1 x 1 1 rfin1 1 x = dont care. rfin0 rfin1 50 ? 50 ? 29 22 0.1 f 1 1990-039 bal_cout reg 0x30[7:5] bal_cin reg 0x30[3:1] rfinx 1 1990-040 rev. 0 | page 14 of 44
data sheet ADRF6820 rf attenuator the rf digital step attenuator ( rf dsa) follows the tunable balun, and the attenuation range is 0 db to 15 db with a step size of 1 db. the rfdsa_sel bits (re gister 0x23, bits[8:5]) in the dga_ctl register determines the setting of the rf dsa. lo generation block the ADRF6820 supports the use of both internal and external lo signals for the mixers. the internal lo is generated by an on - chip vco, which is tunable over an octave frequency range of 2850 mhz to 570 0 mhz. the output o f the vco is phase locked to an external reference cl ock through a fractional - n pll that is programmable through the spi control registers. to produce in - phase and quadrature phase lo signals over the 356.25 to 2850 mhz frequency range to drive the mixers, steer t he vco outputs through a combination of frequency dividers , as shown in figure 32. alternatively, an external signal can be used with the divi ders or a polyphase phase splitter to generate the lo signals in quadrature to the mixers. in demanding applications that require the lowest possible phase noise performance, it may be necessary to so urc e the lo signal externally. the different methods in quadrature lo generation and the control register programming needed are listed in table 9 . internal lo mode for internal lo mode, the ADRF6820 use s the on - chip pll and vco to synthesize the frequency of the lo signal. the pll, shown in figure 32 , consists of a reference path, phase and frequency detector (pfd), charge pump, and a programmable integer divider with prescaler. the reference path takes in a reference clock and divides it down by a factor of 1, 2, 4, or 8 or multiplies it by a factor of 2 , and then passes it to the pfd. the pfd compares this signal to the divided down signal from the vco. depending on the pfd polarity selected, the pfd sends an up/down signal to the charge pump if the vco signal is slow/fast compared to the reference frequency. the charge pump sends a current pulse to the off - chip loop filter to increase or decrease the tuning voltage (vtune). the ADRF6820 integrates four vco cores covering an octave range of 2.85 ghz to 5.7 ghz. table 9 lists the frequency range covered by each vco. the de sired vco can be selected by addressing the vco_sel bits (register 0x22, bits[2:0]). figure 32 . lo generation block diagram table 9 . lo mode selection lo selection f vco or f ext (ghz) quadrature generation quad_div_en , reg ister 0x01[9] lo enables , reg ister 0x01[6:0] vco_sel , reg ister 0x22[2:0] internal (vco) 2.85 to 3.5 div ide by 2 1 111 111 x 011 3.5 to 4.02 divide by 2 1 111 111 x 010 4.02 to 4.6 divide by 2 1 111 111 x 001 4.6 to 5.7 divide by 2 1 111 111 x 000 external (2 lo) 0.7 to 6.0 divide by 2 1 101 000 x 1 xx external (1 lo) 0.35 to 3.5 polyphase 0 000 000 x xxx + pfd charge pum p quad divider cp 2 n = int + frac mod pol yphase fi l ter 1, 2, 4 loin? vtune externa l loo p fi l ter lpf loin+ vco_se l reg 0x22[2:0] div8 _en/ div4_en reg 0x22[4:3] div_mode: reg 0x02[ 1 1] int_di v : reg 0x02[10:0] frac_di v : reg 0x03[15:0] mod_di v : reg 0x04[15:0] cp_ctr l reg 0x20[13:0] 1 2 8 4 2 refin refsel reg 0x21[2:0] pfd_polarity reg 0x21[3] t o mixer i+ i? q+ q? quad_div_en reg 0x01[9] 1 1990-041 35 37 39 32 34 rev. 0 | page 15 of 44
ADRF6820 data sheet lo frequency and dividers the signal coming from the vco or the external lo inputs go es through a series of dividers before it is buffered to drive the active mixers. two programmable divide - by - two stages divide the frequency of the incoming signal by 1, 2, or 4 before reaching the quadrature divider that furthe r divides the signal frequency by two to generate the in - phase and quadrature - phase lo signals for the mixers. the control bits (register 0x22, bits[4:3]) needed to select the different lo frequency ranges are listed in table 10. table 10 . lo frequency and dividers lo frequency range (mhz) f vco / f lo or f ext lo / f lo div8_en (register 0x22, bit 4) div4_en (register 0x22, bit 3) 1425 to 2850 2 0 0 712.5 to 1425 4 0 1 356.25 to 712.5 8 1 1 pll frequency programming the n divider divides down the differential vco signal to the pfd fr equency. the n divider can be configured for fractional or integer mode by addressing the div_mode bit (register 0x02, bit 11). the default configuration is set for fractional mode. use the following equations t o determine the n value and pll frequency: n f f vco pfd = 2 mod frac int n + = lo_divider n f f pfd lo = 2 where: f pfd is the phase frequency detector frequency. f vco is the vco frequency. n is the fractional divide ratio ( int + frac / mod ) . int is the integer divide ratio programmed in register 0 x 02. frac is the fractional divider programmed in register 0 x 03. mod is the modulus divide ratio programmed in register 0 x 04. f lo is the lo frequency going to the mixe r core when the loop is locked. lo_divider is the final frequency divider ratio that divides the f requency of the vco or the external lo signal down by 2, 4, or 8 before it reaches the mixer , as shown in table 10. pll lock t ime the time it takes to lock the pll after the last register is written bre aks down into two parts: vco band c alibration and loop settling. after writing to the last register, the pll automatically perform s a vco band calibration to choose the correct vco band. this cali bration takes approximately 94 , 208 pfd cycles. for a 40 mhz f pfd , this corresponds to 2.36 ms . after calibration complete s, the feedback action of the pll cause s the vco to lock to the correct frequency eventually . the speed with which this lock occurs depends on the no nlinear cycle slipping behavior, as well as the smal l signal settling of the loop. for an accurate estimation of the lock time, download the adisimpll tool to capture these effects correctly . in general, higher bandwidth loops tend to lock more quickly than lower bandwidth loop s. the lock detect signal is available as one of the selectable outputs through the muxout pin, with a logic high signifying that the loop is locked. the control for the muxout pin is located in the ref_mux_sel bits (register 0x21, bits[6:4]), and the default configuration is for pll lock detect. buffered lo outputs a buffered version of the internal lo signal is available differentially at the loo ut+ and loo ut? pins (pin 17 and pin 18). when the quadrature lo signals are generated using the quadrature divider , the output signal is available at either 2 or 1 the frequency of the lo signal at the mixer. set t he output to different drive levels by accessing the lo_drv_lvl bits (register 0x22, bits[ 7 :6 ]), as shown in table 11. th e availability of the lo signal makes it possible to daisy - chain many devices synchronously. one ADRF6820 device can serve as the master where the lo signal is sourced, and the subsequent slave devices share the same lo output signal from the master. this flexibility substantially eases the lo requirements of a system requiring multiple los. table 11 . lo output level lo_drv_lvl (reg ister 0x22 , bits[ 7 : 6 ] ) amplitud e (dbm) dc level (v) 00 ? 5 3.0 01 ? 1 2.85 10 +2 2.7 11 + 4 2.5 external lo mode use the vco_sel bits (register 0x22, bits[2:0]) to s elect external or internal lo mode. to configure for external lo mode, set register 0x22, bits[2:0] to 4 decimal ) and apply the differential lo signals to pin 34 (loin ? ) and pin 35 (loi n+ ). the external lo frequency range is 350 mhz to 6 ghz. w hen the polyphase phase splitter is selected, a 1lo signal is required for the active mixer , or a 2 lo can be used with the inte rnal quadrature divider , as shown in table 9 . t he loin+ and loin ? input pins must be ac - coupled . when not in use, leave the loin+ and loin? pins unconnected . rev. 0 | page 16 of 44
data sheet ADRF6820 required pll/vco settings and register write sequence in addition to writing to the necessary registers to configure the pll and vco for the desired lo frequency and phase noise performance, the registers in table 12 are required register writes . to ensure that the pll locks to the desired frequency, follow the proper write sequence of the pll registers. configure the pll registers accordingly to achieve the desired frequency, and the last writes must be to register 0x02 (int_div), register 0x03 (frac_div), or register 0x04 (mod_div). when register 0x02, register 0x03, and register 0x04 are programmed, an internal vco calibration ini tiates, which is the last step to locking the pll. table 12 . required pll/vco register writes address[bits] bit name setting description 0x21[3] pfd _polarity 0x1 negative polarity 0x49[15:0] reserved, set_1, set_0 0x14b4 internal s ettings active mixers t he signal from the rf dsa is split to drive a pair of double balanced, gilbert cell active mixers , to be downc onverted by the lo signals to baseband. program t he current in the mixers by changing the value of the mix_bias bits (regi ster 0x31, bits[12:10]) for trade - off between output noise and linearity. the active mixers employ a distortion correction circuit for cance lling the third - order distortions coming from the mixers. determine t he amplitude and phase of the correction signal s by the combination of control register entries demod_rdac and demod_cdac ( register 0x31, bits[8:5] and register 0x31, bits[3:0] , respectively ). refer to the ip3 and noise figure optimization section for more information. demodulator gain and bandwidth are set by t he resistance and capacitance in the mixer loads , which are controlled by the bwsel bits (register 0x34, bits[9:8]) according to table 15. refer to the bandwidth select modes for more information baseband buffers emitter followe rs buffer the signals at the mixer loads and drive the baseband output pins ( i + , i ? , q ?, and q+ ). bias currents of the emitter followers are controlled by the bb_bias bits (register 0x34, bits[11:10]) , as shown in table 13. set t he bias current according to the load driving capabilities needed ( that is, bb_bias = 1 for the specified 200 ? load, and bb_bias = 2 for the 50 ? or 100 ? loads are recommended). the d ifferential impedance of t he baseband outputs is 50 ? ; however , the ADRF6820 output load must be high (that is, 200 ? ) for optimized linearity performance. refer to the i/q output loading section for supporting data. table 13. baseband buffer bias bb_bias (register 0x34 , bits [11:10]) bias current (ma) 00 0 01 4.5 10 9 11 13.5 serial port interfac e (spi) the spi of t he ADRF6820 allows the user to configure the device for specific functions or operations through a structured register space provided inside the chip. this interface provides user s with added flexibility and customization. addresses are accessed via the serial port interface and can be written to or read from via the serial port interface. the serial port interface consists of three control lines: sclk, sdio, and cs . sclk (serial clock) is the serial shift clock , and it synchronizes the serial interface reads and writes. sdio is the serial data input or the serial data outp ut depending on the instruction sent and the relative position in the timing frame. cs (chip select bar) is an active low control that gates the read and write cycles. the falling edge of cs in conjunction with the risin g edge of sclk determines the start of the frame. when cs is high, a ll sclk and sdio activity is ignored. see table 4 for the serial timing and its d efinitions. the ADRF6820 protocol consists of seven register address bits, followed by a r ead/ write and 16 data bits. both the address and data fields are organized with the most significant bit ( msb ) first and end with the least significant bit ( lsb ) . on a write cycle, up to 16 bits of serial write data is shifted in, msb to lsb. if the rising edge of cs occurs before the lsb of the serial data is latched , only the bits that were latched are written to the device. if more than 16 data bits are shifted in, the 16 most recent bits are written to the device. the ADRF6820 input logic level for the write cycle supports an interface as low as 1.8 v. on a read cycle, up to 16 bits of serial read data is shifted out, msb first . data shifted out beyond 16 bits is undefined. read back content at a given register address does not necessarily correspond wi th the write data of the same address. the output logic level for a read cycle is 2.5 v. rev. 0 | page 17 of 44
ADRF6820 data sheet applications information b a sic connections figure 33 . basic connections table 14. pin no. mnemonic description basic connection 5 v power 11 v pos _5v mixer power supply decouple this power supply pins via a 100 pf and 0.1 f capacitor to ground. ensure that the decoupling capacitors are located close to the pin. 21 v pos _ 5v rf front - end power supply decouple this power supply pin via a 100 pf and 10 f (0805) capacitor to ground. ensure that the decoupling capacitors are located close to the pin. 3.3 v power 1 v pos _3p3v digital power supply decouple this pin via a 100 pf and 0.1 f capacitor to ground . 19 v pos _3p3v lo power supply decouple this pin via a 100 pf and 0.1 f capacitor to ground . 30 v pos _3p3v lo power supply decouple this pin via a 100 pf and 0.1 f capacitor to ground . 31 v pos _3p3v vco power supply decouple this pin via a 100 pf and 10 f capacitor to ground . 36 v pos _3p3v pll power supply decouple this pin via a 100 pf and 0.1 f capacitor to ground . 8 lock_det vptat scan + pfd charge pum p cp 2 frac mod refin muxout cs sclk sdio loin? loin+ cp ldo vco seria l port inter f ace vocm vpos_3p3 vpos_5v vtune 1, 2, 4 div 2 phase splitter 0 90 1, 2 pol yphase fi l ter 1 3 6 4 49.9? (0402) decl1 decl4 decl3 decl2 vpos_3p3 tc1-1-43a+ i? i+ tc4-1w+ 3 1 2 6 4 q? q+ tc4-1w+ 3 1 2 6 4 dc/phase correction dc/phase correction 0? (0402) 0? (0402) 100pf (0402) 100pf (0402) loout+ loout? 1 3 6 4 100pf (0402) 100pf (0402) 100pf (0402) 49.9? (0402) 5.1k? (0402) 10k? (0402) 10k? (0402) 22pf (0402) 6.8pf (0402) 2.7nf (0402) 3k? (0402) 22pf (0402) n = int + ldo 2.5v mixer buffer 3.3/5.0v 100pf (0402) 10 f (0805) 100pf (0402) 0.1 f (0805) 100pf (0402) 0.1 f (0402) 100pf (0402) 0.1 f (0402) 100pf (0402) 0.1 f (0402) 100pf (0402) 10 f (0805) 100pf (0402) 10 f (0805) 100pf (0402) 10 f (0805) 100pf (0402) 10 f (0805) 0.22 f (0402) 100pf (0402) 0.1 f (0402) 4 2 3 8 9 23 25 26 28 38 5 7 6 34 35 32 37 12 21 11 19 30 36 31 27 33 40 10 1 vcc_3p3 enb l pwr_dwn enable 24 vcc_3p3 rfsw rfin0 rfin1 20 15 14 13 rfin0 rfin1 1000pf (0402) 1000pf (0402) 29 22 17 18 39 16 4 2 1 2 1 1990-042 rev. 0 | page 18 of 44
data sheet ADRF6820 pin no. mnemonic description basic connection pll/vco 3 7 cp synthesizer charge pump output voltage connect to the vtune pin through the loop filter. 39 refin synthesizer reference frequency input nominal input lev el is 1 v p - p. input range is 12 mhz to 320 mhz. this pin is internally biased to v pos _3p3v/2 and must be ac - coupled. 17, 18 loo ut+ , loo ut? differential lo outputs the differential output impedance is 50 . these p ins are internally biased and must be ac - coupled . the dc level var ies with lo output drive level. refer to table 11. 3 4, 3 5 loin ? , loi n+ differential lo inputs differential input impedance of 50 . these p ins are internally biased and must be ac - coupled. 16 muxout pll multiplex output this o utput pin provides the pll reference signal or the pll lock detect signal . 32 vtune vco tuning voltage this pin is driven by the output of the loop filter, and the no minal input voltage range is 1 v to 2.8 v. rf inputs 22, 29 rfin1, rfin0 rf inputs the single - ended rf inputs have a 50 input impedance. th ese pin s are internally biased to v pos _5v/2. ac couple the rf inputs. refer to the layout section for the recommended printed circuit board ( pcb ) layout for improved channel -to - channel isolation. terminate unused rf inputs with a dc blocking capacitor to gnd to improve on isolatio n. 20 rfsw pin control of the rf inputs for rfin0 , set rfsw to logic low , and for rfin1 , set rfsw to logic high. for logic high , connect the pin to 2.5 v . demodulator output s 4, 5, 6, 7 i + , i ? , q? , q+ i and q channel mixer baseband outputs the i and q mixer outputs have a 50 differential output impedance (25 per pin). the vocm pin sets the output common - mode level. 12 vocm mixer output common - mode voltage t he input pin sets the common - mode voltage of the i and q complex outputs. vocm needs a clean voltage source within the 1.5 v to 2. 4 v range. linearity performance degrades when the voltage i s outside this range. enable 24 enbl external enable pin control set this pin high for enab le and low for power - down of the internal blocks. to specify th e internal blocks , write to r egister 0x10 , power - down mask. serial port interface 13 sdio spi data input and output 3.3 v tolerant logic levels. 14 sclk spi clock 3.3 v tolerant logic levels. 15 cs spi chip select active low. 3.3 v tolerant logic levels. ldo decoupling 10 decl1 mixer ldo decoupling d ecouple this pin via 0.22 f capacitor to ground. ensure the decoupling capacitor is located close to the pin . 2 7 decl2 vco2 ldo decoupling decouple this power supply pin via 100 pf and 10 f (0805) capacitor s to ground. ensure that the decoupling capacitors are located close to the pin. 33 decl3 vco ldo decoupling decouple this power supply pin via 100 pf and 10 f (0805) capacitors to ground. ensure that the decoupling capacitors are located close to the pin. 40 decl4 2.5v ldo decoupling decouple this power supply pin via 100 pf and 10 f capacitor s to ground. ensure that the decoupling capacitors are located close to the pin. gnd connect these pins to the gnd of pcb . 2, 3, 8, 9, 23, 25, 26, 28, 38 gnd ground (epad) exposed pad (epad) the exposed thermal pad is on the bottom of the package. solder t he exposed pad to ground. rev. 0 | page 19 of 44
ADRF6820 data sheet rf balun insertion l oss optimization as shown in figure 34 to figure 37 , the gain of the ADRF6820 mixer was characterized for every combination of bal_cin and bal_cout (register 0x30 , bits[7:0] ). as shown, a range of bal_cin and bal_cout values can be used to optimize the gain of th e ADRF6820 . the optimized values do not change with temperature. after the values are chosen, the absolute g ain changes over tem perature; however, the signature of the bal_cin and bal_cout values is fixed. at lower input frequencies, more capacitance is needed. this capacitance increase is achieved by programming higher codes into bal_cin and bal_cout. at higher frequencies, less capacitance is required ; therefore, lower bal_cin and bal_cout codes are appropriate. figure 38 shows the change in gain over frequency for various bal_cin and bal_cout codes. use figure 34 to figure 38 only as guides; do not interpret them in the absolute sense because every application and pcb design var y . additional fine - tuning may b e necessar y to achieve the maximum gain. table 16 shows the recommended bal_cin and bal_cout settings for various rf frequencies. figure 34 . gain vs. bal_cin and bal_cout at f rf = 900 mh figure 35 . gain vs. bal_cin and bal_cout at f rf = 2200 mhz figure 36 . gain vs. bal_cin and bal_cout at f rf = 1900 mhz figure 37 . gain vs. bal_cin and bal_cout at f rf = 2600 mhz ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 gain (db) c in /c out ?40c +25c +85c 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 1990-025 c in c out gain (db) c in /c out ? 10 ? 9 ? 8 ? 7 ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ?40c +25c +85c 1 1990-026 c in c out gain (db) c in /c out ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ?40c +25c +85c 1 1990-027 c in c out gain (db) c in /c out c in c out ? 16 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 ?40c +25c +85c 1 1990-028 rev. 0 | page 20 of 44
data sheet ADRF6820 figure 38 . gain vs. rf frequency for various bal_cin and bal_cout codes ?12 ?10 ?8 ?6 ?4 ?2 0 500 700 900 1 100 1300 1500 1700 1900 2200 2400 2600 gain (db) rf frequenc y (mhz) 1 1990-029 cin = 0, cout = 0 cin = 1, cout = 1 cin = 2, cout = 2 cin = 3, cout = 3 cin = 4, cout = 4 cin = 5, cout = 5 cin = 6, cout = 6 cin = 7, cout = 7 rev. 0 | page 21 of 44
ADRF6820 data sheet bandwidth select mod es the ADRF6820 offers four ba ndwidth select modes , as specified in table 15. the bandwidth select modes include either high gain and low bandwidth or low gain and high bandwidth. it is the selection of the resistance and capacitance in the mixer load that determines the if gain and bandwidth. use r egister 0x34, b its[9:8] to select one of the four modes. t he high gain mode s , bw s el0 and bwsel1, ha ve equivalent per formance in terms of gain, noise figure, and linearity. similarl y , the low gain modes, bwsel2 and bwsel 3 , share the same performance specification s . however, the factor that distinguishes the different modes is the if bandwidth. figure 39 to figure 42 show th e voltage gain, pass - band flatness, and 1 db bandwidth of the bandwidth modes for the various lo frequencies. table 15 summarizes the results of figure 39 to figure 42. table 15 . mixer gain and bandwidth select modes 1 bwsel (reg. 0x34[9:8]) mode voltage gain (db) 1 db bw (mhz) 3 db bw (mhz) 00 bwsel0 +2 240 480 01 bwsel1 +2 180 340 10 bwsel2 ? 3 600 1400 11 bwsel3 ? 3 500 900 1 f lo = 2100 mhz, high - side lo injection. the lo frequency was set to 1800 mhz, 2100 mhz, and 2700 mhz , and the rf frequency was swept. with this measurement approach, figure 39 to figure 42 show the eff ects of both the rf and if roll - off. the rf roll - off is determined by the integrated rf balun , and the if roll - off is set by the bandwidth select mode. the effect of both the rf roll - off and if roll - off is most evident in the widest bandwidth mode ( bwsel2 ), as shown in figure 41. figure 41 shows the flattest and widest bandwidth when the lo frequency is at 2700 mhz because the rf frequency is farthest from the roll - off of the integrated rf balun. in the f lo = 1800 mhz and f lo = 2100 mhz sweeps, the effect of the rf balun becomes evident resulting in a narrower 1 db bandwidth . it is very difficult to accurately measure the voltage gain flatness of the ADRF6820 because the signal gene rators and spectrum analyzers introduce their own amplitude inaccuracies. additionally , at higher frequencies, the board traces are not as well matched , resulting in signal reflections. with the amplitude errors /inaccuracies from the signal generators and spectrum analyzers included in the measurement, the gain flatness of the ADRF6820 is approximate ly 0.3 db for any 100 mhz bandwidth or approximately 0.2 db for any 20 mhz bandwidth. by design, the gain flatness of the ADRF6820 is substantially better than this ; however , the measurement approach is the limiting factor , and the result is quoted as such. figure 39 to figure 42 show data for both positive and negative if frequencies; positi ve if frequencies represent low - side lo injection , and nega tive frequencies represent high - side lo injection. figure 39 . voltage gain vs. if frequency, bwsel = 0, lo fixed and rf swept figure 40 . voltage gain vs. if frequency, bwsel = 1, lo fixed and rf swept lo = 1800 mhz lo = 2100 mhz lo = 2700 mhz ?300 ?200 ?100 0 100 200 300 volt age gain (db) if frequenc y (mhz) 1 1990-013 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?300 ?200 ?100 0 100 200 300 if frequenc y (mhz) vo lt age gain (db) lo = 1800mhz lo = 2100mhz lo = 2700mhz 1 1990-012 rev. 0 | page 22 of 44
data sheet ADRF6820 figure 41 . voltage gain vs. if frequency, bwsel = 2, lo fixed and rf swept figure 42 . voltage gain vs. if frequency, bwsel = 3, lo fixed and rf swept ?8.0 ?7.5 ?7.0 ?6.5 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?800 ?600 ?400 ?200 0 200 400 600 800 if frequenc y (mhz) volt age gain (db) lo = 1800mhz lo = 2100mhz lo = 2700mhz 1 1990-0 1 1 ?8.0 ?7.5 ?7.0 ?6.5 ?6.0 ?5.5 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 ?800 ?600 ?400 ?200 0 200 400 600 800 if frequenc y (mhz) volt age gain (db) lo = 1800mhz lo = 2100mhz lo = 2700mhz 1 1990-010 rev. 0 | page 23 of 44
ADRF6820 data sheet ip3 and noise figure opti mization the ADRF6820 can be configured for either improved per formance or reduced power consumption. in applications where performance is critical, the ADRF6820 offers ip3 or noise figure optimization. however, if power consumption is the priority , the mixer bias current can be reduced to save on overall power at the expense of degraded perform ance. depending on the application specific needs, the ADRF6820 offers configurability that balances performance and power consumption. adjustments to the mixer bias setting have the most impa ct on performance and power. for this reason, first adjust the mixer bias . the active mixer core of the ADRF6820 is a linearized transco nductor. with increased bias current, the transconductor becomes more linear, resulting in higher ip3. the higher ip3, however, is at the expense of degraded noise figure and increased power consumption. for a 1 - bit change of the mixer bias (mix_bias, register 0x31, bits[12:10 ]), the total mixer current increas es by 8 ma . inevitably, there is a limit on how much the bias current can increase before the improvement in linearity no longer justifies the increase in power and noise. the mixer core reach es a point where further increases in bias current do not transl ate to improved linearity performance. when that point is reached, decrease the bias current to a level where the desired performance is achieved. depending on the system specifications of the customer, a balance between linearity, noise figure, and power can be attained. in addition to bias optimization, the ADRF6820 also has configurable distortion cancellation circuitry. the linearized transconductor input of the ADRF6820 is composed of a main path and a secondary path. through adjustments of the amplitude a nd phase of the secondary path, the distortion generated by the main path can be canceled, resulting in improved ip3 performance . the amplitude and phase adjustments are located in the following serial inter face bits: demod _rdac (register 0x31, bits[8:5]) and demod _cdac (register 0x31, bits[3:0]). figure 43 to figure 46 show the input ip3 and noise figure sweeps for all demod _ rdac, demod _ cdac, and mix_bias combi nations. the input ip3 vs. demod _ rdac and demod _ cdac figures show both a surface and a contour plo t in one figure. t he contour plot is located directly underneath the surface plot. the best approach for r eading the figure s is to locate the peaks on the surfac e plot, which indicate maximum input ip3, and to follow the same color pattern to the contour p lot to determine the optimized demod _ rdac and demod _ cdac values. the overall shape of the input ip3 plot does not vary with the mix_bias setting; therefore, only mix_bias = 011 is displayed. table 16 shows the recommended mix_bias, demod_rdac, and demod_cdac settings for various rf frequencies. use table 16 and figure 43 to figure 46 as guides only; do not interpret them in the absolute sense because every application and input signal var y . figure 43 . iip3 vs. de mod_ cdac and demod_ rdac, mix_ bias = 3 at f rf = 900 mhz figure 44 . iip3 vs. demod_cdac and demod_rdac, mix_bias = 2 at f rf = 1900 mhz 0 5 10 15 0 10 20 25 30 35 40 rdac cdac iip3 (dbm) 26 28 30 32 34 36 38 1 1990-031 0 5 10 15 0 5 10 15 20 25 30 35 40 cdac rdac iip3 (dbm) 24 26 28 30 32 34 36 38 1 1990-032 rev. 0 | page 24 of 44
data sheet ADRF6820 rev. 0 | page 25 of 44 figure 45. iip3 vs. demod_cdac and demod_rdac, mix_bias = 2 at f rf = 2100 mhz figure 46. iip3 vs. demod_cdac and demod_rdac, mix_bias = 2 at f rf = 2700 mhz recommended settings for bal_cin, bal_cout, mix_bias, demod_rdac, and demod_cdac settings table 16. recommended settings bwsel f rf (mhz) bal_ cin bal_ cout mix_ bias demod_ rdac demod_ cdac 0 500 7 7 2 9 10 0 600 7 7 2 9 10 0 700 7 7 2 8 11 0 800 7 3 2 9 4 0 900 6 2 1 8 7 0 1000 5 1 1 8 9 0 1100 3 2 1 9 6 0 1200 3 1 1 8 8 0 1300 2 1 2 8 7 0 1400 2 1 2 9 3 0 1500 1 1 2 9 4 0 1600 1 1 1 8 5 0 1700 1 0 1 8 5 0 1800 1 1 1 8 6 0 1900 1 0 1 8 5 0 2000 1 0 2 8 4 0 2100 1 0 2 8 4 0 2200 1 0 2 9 2 0 2300 1 0 2 9 3 0 2400 1 0 2 7 3 0 2500 1 0 2 7 3 0 2600 1 0 2 7 3 0 2700 1 0 1 8 4 0 2800 1 0 1 8 4 bwsel f rf (mhz) bal_ cin bal_ cout mix_ bias demod_ rdac demod_ cdac 2 500 7 7 3 5 7 2 600 7 7 3 5 7 2 700 7 7 2 4 9 2 800 7 3 3 8 4 2 900 6 2 3 9 5 2 1000 5 1 3 7 7 2 1100 3 2 2 6 9 2 1200 3 1 2 8 9 2 1300 2 1 2 3 9 2 1400 2 1 3 8 5 2 1500 1 1 3 8 6 2 1600 1 1 2 8 5 2 1700 1 0 2 8 5 2 1800 1 1 2 8 7 2 1900 1 0 2 5 6 2 2000 1 0 3 5 7 2 2100 1 0 2 4 6 2 2200 1 0 2 4 6 2 2300 1 0 3 8 6 2 2400 1 0 3 8 6 2 2500 1 0 3 9 6 2 2600 1 0 3 9 6 2 2700 1 0 2 8 5 2 2800 1 0 2 8 5 0 5 10 15 0 5 10 15 20 22 24 26 28 30 32 34 36 38 c d a c r d a c iip3 (dbm) 22 24 26 28 30 32 34 36 11990-033 0 10 20 0 5 10 15 20 25 30 35 40 c d a c r d a c iip3 (dbm) 22 24 26 28 30 32 34 36 38 11990-034
ADRF6820 data sheet i/q output loading the i and q baseband outputs of the ADRF6820 have a 50 ? differential impedance . however, voltage gain and linearity performance are optimized with the use of a 200 ? differential load. this may n ot be the most fav orable ter mination for every application; therefore, performance trade - offs can be made for lower output loads. the output load on the differential i/q outputs has a direct impact on the voltage gain where the gain decrease s with lighter loads. the 50 ? differential source impedance ( r s ) of the ADRF6820 forms a voltage divider with the external load resistor ( r l ) . the performance of the ADRF6820 was optimized for a nd specified with a differential load termination of 200 ? . f or a 200 ? differential load termination, the voltage divider ratio is given by v out / v in = r l /( r l + r s ) where r s = 50 ?. the change in gain due to different load impedance is given by ( ) ( ) s l1 l1 s l2 l2 l1 l2 r r r r r r r gain r gain + + = ) ( ) ( where: r l1 = 200 ? . r l2 is the new load impedance . the conversion gain of the ADRF6820 at f rf = 2100 mhz and f if = 200 mhz is ? 3.2 db. for the same test conditions with a 100 ? load , the gain decreases by 20log(5/6) = ? 1.58 db to a voltage gain of ? 4.6 db. figure 47 shows the v oltage gain vs. if frequency for f lo = 1840 mhz and bwsel = 2 for common output loads. figure 47 . voltage gain vs. if f requency for lo = 1840 mhz , bwsel = 2 in addition to the lower conver sion gain, the effect of lower output loa d impedance is degraded linearity performance. the degraded perform ance is a result of the emitter follower buffers, after the mixers , needing to deliver more load current; therefore , they operate closer to their nonlinear region. t o improve performance with lighter loads, such as 50 ?, increase the bias current of the emitter follower by increasing bb_bias ( r egister 0x34, bits[11:10]) to its maximum of 13.5 ma. refer to table 13 for the bias current settings. figure 48 . iip3 and i ip2 vs. if f requency for f lo = 1840 mhz and bwsel = 2 figure 48 shows input ip3 and input i p2 performance vs . if frequency for 50 ?, 100 ?, and 200 ? loads. for the 100 ? and 200 ? load impedance , the bias current was configured to its default of 9 ma , wh e reas for the 50 ? load , the current was increased to the maximum to achieve the same level of input ip3 performance as the higher output loads. ?13 ?12 ? 1 1 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 10 30 50 70 90 1 10 130 150 170 190 210 230 250 270 290 310 330 350 370 390 410 430 450 470 490 510 530 550 570 590 610 630 650 670 690 710 730 750 770 790 810 830 850 870 volt age gain (db) if frequenc y (mhz) r l ? r l ? r l ? 1 1990-140 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 1 0 3 0 5 0 7 0 9 0 1 1 0 13 0 15 0 17 0 19 0 21 0 23 0 25 0 27 0 29 0 31 0 33 0 35 0 37 0 39 0 41 0 43 0 45 0 47 0 49 0 51 0 53 0 55 0 57 0 59 0 61 0 63 0 65 0 67 0 69 0 71 0 ii p 3 ( d b m ) , ii p 2 ( d b m ) i f f r e q u e n cy (m h z) ii p 3 = 5 0 ? ii p 3 = 10 0 ? ii p 3 = 20 0 ? ii p 2 = 5 0 ? ii p 2 = 10 0 ? ii p 2 = 20 0 ? 11990-141 rev. 0 | page 26 of 44
data sheet ADRF6820 image rejection the a mplitude and phase mismatch of the baseband i and q p aths directly translates to degradations in image rejection , and fo r direct conversion systems , maximizing image rejection is key to achieving performance and optimizing bandwidth. the ADRF6820 offers phase adjustment of the i and q paths independently to allow for quadrature correction. the quadrature correction can be accessed by writing to r egister 0x32 , bits [3:0] for the i path correction and register 0x32, b its[7:4] for the q path c orrection. figure 49 shows the available correction range for various lo frequencies. use the following equation t o translate the gain and quadrature phase mismatch to image rejection ratio (irr) performance. ( ) ( ) ( ) e e 2 e e e 2 e a a a a db irr ? ? + ? + + = cos 2 1 cos 2 1 log 10 where: a e is the amplitude error. e is the phase error. one of the dominant sources of phase error in a system originates from the demodulator where the quadrature phase split of the lo signal occurs. figure 50 to figure 52 show the level of image rejection achievable from the ADRF6820 across different sweep parameters with no correction applied. figure 49 . quadrature correction range figure 50 . image rejection vs. rf frequency, f if = 200 mhz figure 51 . image rejection vs. rf signal level, if = 200 mhz , for high - side lo i njection f lo = 2000 mhz and f rf = 1800 mhz and vice versa for low - side injection figure 52 . image rejection vs. if frequency, f lo = 1800 mhz 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 phase error (degrees) ilo or qlo setting 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 1 1990- 1 13 ilo adjust lo = 740mhz lo = 940mhz lo = 1940mhz lo = 2540mhz qlo adjust 2.9 2.5 1.1 0.9 25 27 29 31 33 35 37 39 41 43 45 700 900 1 100 1300 1500 1700 1900 2100 2300 2500 2700 image rejection (db) rf frequenc y (mhz) high-side lo: int 2 lo high-side lo: ex t . 1 lo, po l yphase lo w -side lo: int 2 lo lo w -side lo: ex t . 1 lo, po l yphase 1 1990-047 25 27 29 31 33 35 37 39 41 43 45 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 image rejection (db) rf sig am p (dbm) lo w -side lo: int 2 lo high-side lo: int 2 lo lo w -side lo: ext 1 lo, po l yphase high-side lo: ext 1 lo, po l yphase 1 1990-148 25 27 29 31 33 35 37 39 41 43 45 0 100 200 300 400 500 600 image rejection (db) externa l lo: po l yphase interna l 2 lo if frequenc y (mhz) 1 1990-049 rev. 0 | page 27 of 44
ADRF6820 data sheet i/q polarity the ADRF6820 offers the flexibility of specifying the polarity of the i/q outputs, where i can lead q or vice versa. by addressing poli ( register 0x32 , bits [9:8] ) or polq ( register 0x32 , bits [11:10]), both the i and q outputs can be inverted from their default configuration. th e flexibility of specifying the polarity becomes important when the i and q outputs are processed simultaneously in the complex domain, i + jq. at power up, depending on whether high - side or low - side injection of the lo frequency is applied, the i channel can either lead or lag the q channel by 90. when the rf frequency is gre ater than the lo frequency (low - side lo injection), the i channel leads the q channel (see figure 53 ). on the contrary, if the rf frequency is less than the lo frequency (high - side lo injection), the q channel leads the i channel by 90 (see figure 54). figure 53 . poli = 1, polq = 2, i channel normal polarity, q channel normal polarity, f rf = 2040 mhz, and f lo = 1840 mhz figure 54 . poli = 1, polq = 2, i channel normal polarity, q channel normal polarity, f rf = 2040 mhz, and f lo = 2240 mhz both the i and q channel s can be inverted to achieve the desired polarity, as shown in figure 55 to figure 57 , by writing to poli ( register 0x32 , bits [9:8]) or polq ( register 0x32 , bits [11:10]). figure 55 . poli = 2, polq = 2, i channel invert polarity, q channel normal pola rity, f rf = 2040 mhz, and f lo = 2240 mhz figure 56 . poli = 1 , polq = 1 , i channel normal polarity, q channel invert polarity, f rf = 2040 mhz, and f lo = 2240 mhz figure 57 . poli = 2, polq = 1 , i channel invert polarity, q channel invert polarity, f rf = 2040 mhz, and f lo = 2240 mhz ? 0.10 ? 0.08 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 0.08 0.10 ?5 ?4 ?3 ?2 ?1 0 time (ns) trigger 1 2 3 4 5 q channe l i channe l 1 1990-135 ? 0.10 ? 0.08 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 0.08 0.10 ?5 ?4 ?3 ?2 ?1 0 time (ns) trigger 1 2 3 4 5 i channe l q channe l 1 1990-136 ? 0.10 ? 0.08 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 0.08 0.10 ?5 ?4 ?3 ?2 ?1 0 time (ns) trigger 1 2 3 4 5 i channe l q channe l 1 1990-137 1 1990-138 ? 0.10 ? 0.08 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 0.08 0.10 ?5 ?4 ?3 ?2 ?1 0 time (ns) trigger 1 2 3 4 5 i channe l q channe l ? 0.10 ? 0.08 ? 0.06 ? 0.04 ? 0.02 0 0.02 0.04 0.06 0.08 0.10 ?5 ?4 ?3 ?2 ?1 0 time (ns) trigger 1 2 3 4 5 i channe l q channe l 1 1990-139 rev. 0 | page 28 of 44
data sheet ADRF6820 layout careful layout of the ADRF6820 is necessary for performance optimization, and it minimizes str ay parasitics. the ADRF6820 supports two rf inputs; therefore, the layout of the rf section is critical in achieving isolation between each channel. figure 58 shows the recommended layout for the rf inputs. each rf input , rfin0 and rfin1 , is isolated between ground pins, and the best layout approach is to keep the traces short and direct. to achieve this, connect the pins directly to the center ground pad of the exposed pad of the ADRF6820 . this approach minimizes the trace inductance and promotes better isolation between the channels. i n addition, for improved isol ation, do not route the rfin0 and rfin1 traces in parallel to each other; split the traces immediately after each one leaves the pins. keep the traces as far away from each other as possible to prevent cross coupling. the inpu t impedance of the rf inputs is 50 ?, and the traces leading to the pin must also have a 50 ? characteristic impedance . for unused rf inputs, terminate the pins with a dc blocking capacitor to ground. figure 58 . recommended rf input layout gnd gnd rfin1 rfin0 gnd 1 1990-048 rev. 0 | page 29 of 44
ADRF6820 data sheet register map table 17. hex addr. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 00 soft_reset [15:8] reserved 0x0000 w [7:0] reserved soft_reset 01 enables [15:8] unused dmod_en quad_div_en lo_drv2x_en 0xfe 7f rw [7:0] lo_drv1x_en vco_mux_ en ref_buf_en vco_en div_en cp_en vco_ldo_en unused 02 int_div [15:8] reserved div_mode int_div[10:8] 0x002c rw [7:0] int_div[7:0] 03 frac_div [15:8] frac_div[15:8] 0x0128 rw [7:0] frac_div[7:0] 04 mod_div [15:8] mod_div[15:8] 0x0600 rw [7:0] mod_div[7:0] 10 pwrdwn_ mask [15:8] unused dmod_ mask quad_div_ mask lo_drv2x_ mask 0xfe 7f rw [7:0] lo_drv1x_ mask vco_mux_ mask ref_buf_ mask vco_ mask div_ mask cp_ mask vco_ldo_ mask unused 20 cp_ctl [15:8] reserved cpsel cscale reserved 0x0c26 rw [7:0] reserved bleed 21 pfd_ctl [15:8] reserved 0x0003 rw [7:0] reserved ref_mux_sel pfd_polarity refsel 22 vco_ctl [15:8] reserved reserved 0x2a03 rw [7:0] lo_drv_lvl drvdiv2_en div8_en div4_en vco_sel 23 dga_ctl [15:8] reserved rfsw_mux reserved rfsw_sel rfdsa_sel[3] 0x0000 rw [7:0] rfdsa_sel[2:0] reserved 30 balun_ctl [15:8] reserved 0x0000 rw [7:0] bal_cout bal_cin 31 mixer_ctl [15:8] reserved mix_bias reserved demod_rdac[3] 0x1101 rw [7:0] demod_rdac[2:0] reserved demod_cdac 32 mod_ctl0 [15:8] reserved polq poli 0x0900 rw [7:0] qlo ilo 33 mod_ctl1 [15:8] dcoffi 0x0000 rw [7:0] dcoffq 34 mod_ctl2 [15:8] reserved bb_bias bwsel 0x0b00 rw [7:0] reserved reserved 40 pfd_ctl2 [15:8] reserved 0x0010 rw [7:0] reserved abldly cpctrl clkedge 42 dith_ctl1 [15:8] reserved 0x000e rw [7:0] reserved dith_en dith_mag dith_val 43 dith_ctl2 [15:8] dith_val[15:8] 0x0001 rw [7:0] dith_val[7:0] 45 vco_ctl2 [15:8] reserved vtune_ctrl 0x0000 rw [7:0] vco_band_src band 49 vco_ctl3 [15:8] reserved set_1[13:9] set_0[8] 0x16bd rw [7:0] set_0[7:0] rev. 0 | page 30 of 44
data sheet ADRF6820 register address des criptions address: 0x00, reset: 0x0000, name: soft_reset table 18 . bit descriptions for soft_reset bits bit name settings description reset access 0 soft_reset soft reset 0x0000 r address: 0x01, reset: 0xfe 7f, name: e nables table 19 . bit descriptions for e nables bits bit name settings description reset access 10 dmod_en dmod enable 0x1 rw 9 quad_div_en quadrature divider path enable (2/4/8 lo) 0x1 rw 8 lo_drv2x_en external 2 lo d ri ver enable before quad divider 0x0 rw 7 lo_drv1x_en external 1 lo d r iver enable after quad divider 0x0 rw 6 vco_mux_en vco mux enable 0x1 rw 5 ref_buf_en refere nce buffer enable 0x1 rw 4 vco_en power up vcos 0x1 rw 3 div_en power up dividers 0x1 rw 2 cp_en power up charge pump 0x1 rw 1 vco_ldo_en power up vco ldo 0x1 rw rev. 0 | page 31 of 44
ADRF6820 data sheet address: 0x02, reset: 0x002c, name: int_div table 20 . bit descriptions for int_div bits bit name settings description reset access 11 div_mode divide mode 0x0 rw 0 fractional 1 integer [10:0] int_div set divider int value 0x2c rw integer mode r a n ge : 21 to 123 fractional mode range: 24 to 119 address: 0x03, reset: 0x0128, name: frac_div table 21 . bit descriptions for frac_div bits bit name settings description reset access [15:0] frac_div set divider frac value 0x128 rw address: 0x04, reset: 0x0600, name: mod_div table 22 . bit descriptions for mod_div bits bit name settings description reset access [15:0] mod_div set divider mod value 0x600 rw rev. 0 | page 32 of 44
data sheet ADRF6820 address: 0x10, reset: 0xfe 7f, name: pwrdwn _ mask table 23 . bit descriptions for pwrdwn_mask bits bit name settings description reset access 10 dmod_mask demodulator (dmod) enable 0x1 rw 9 quad_div_mask quadrature divider path enable (2/4/8 lo) 0x1 rw 8 lo_drv2x_mask external 2 lo d ri ver enable before quad divider 0x0 rw 7 lo_drv1x_mask external 1 lo d r iver enable after quad divider 0x0 rw 6 vco_mux_mask vco mux enable 0x1 rw 5 ref_buf_mask reference buffer enable 0x1 rw 4 vco _mask power up vcos 0x1 rw 3 div_mask power up divi ders 0x1 rw 2 cp_mask power up charge pump 0x1 rw 1 vco_ldo_mask power up vco ldo 0x1 rw rev. 0 | page 33 of 44
ADRF6820 data sheet address: 0x20, reset: 0x0c26, name: cp_ctl table 24 . bit descriptions for cp_ctl bits bit name settings description reset access 14 cpsel charg e pump reference current select 0x0 rw 0 internal charge pump 1 external charge pump [13:10] cscale c harge pump coarse scale current 0x3 rw 0001 250 a 0011 500 a 0111 750 a 1111 1000 a [5:0] bleed charge pump bleed 0x26 rw 000000 0 a 000001 15.625 a sink 000010 31.25 a sink 000011 46.875 a sink ... 011111 484.375 a sink 100000 0 a 100001 15.625 a source 100010 31.25 a source 100011 46.875 a source ... 111111 484.375 a source rev. 0 | page 34 of 44
data sheet ADRF6820 address: 0x21, reset: 0x0003, name: pfd_ctl table 25 . bit descriptions for pfd_ctl bits bit name settings description reset access [6:4] ref_mux_sel reference ( ref ) mux select 0x0 rw 000 lock_det 001 vptat 010 refclk 011 refclk/2 100 refclk 2 101 refclk/8 110 refclk/4 111 scan 3 pfd_polarity set pfd polarity 0x0 rw 0 p ositive 1 n egative [2:0] refsel set ref input mult iply /div ide ratio 0x3 rw 000 2 001 1 010 divide by 2 011 divide by 4 100 divide by 8 rev. 0 | page 35 of 44
ADRF6820 data sheet address: 0x22, reset: 0x2a03, name: vco_ctl table 26 . bit descriptions for vco_ctl bits bit name settings description reset access [7:6] lo_drv_lvl external lo amplitude 0x0 rw 00 ? 5 dbm 01 ? 1 dbm 10 +2 dbm 11 +4 dbm 5 drvdiv2_en div ide by 2 for e xtern al lo driver enable 0x0 rw 0 disable 1 enable 4 div8_en divide by 2 in lo path for total of division of 8 0x0 rw 0 disable 1 enable 3 div4_en divide by 2 in lo path for total of division of 4 0x0 rw 0 disable 1 enable [2:0] vco_sel select vco core/external lo 0x3 rw 000 4.6 ghz to 5.7 ghz 001 4.02 ghz to 4.6 ghz 010 3.5 ghz to 4.02 ghz 011 2.85 ghz to 3.5 ghz 100 ext ernal lo/vco rev. 0 | page 36 of 44
data sheet ADRF6820 address: 0x23, reset: 0x0000, name: dga_ctl table 27 . bit descriptions for dga_ctl bits bit name settings description reset access 11 rfsw_mux rf switch mux 0x0 rw 0 pin control (cntrl) 1 serial control (cntrl) 9 rfsw_sel rf switch select 0x0 rw 0 rfin0 1 rfin1 [8:5] rfdsa_sel rfdsa s election 0x0 rw 0000 0 db 0001 1 db 0010 2 db 0011 3 db 0100 4 db 0101 5 db 0110 6 db 0111 7 db 1000 8 db 1001 9 db 1010 10 db 1011 11 db 1100 12 db 1101 13 db 1110 14 db 1111 15 db rev. 0 | page 37 of 44
ADRF6820 data sheet address: 0x30, reset: 0x0000, name: balun_ctl table 28 . bit descriptions for balun_ctl bits bit name settings description reset access [7:5 ] bal_cout balun output capacitance 0x0 rw 000 min imum cap acitance value 111 max imum capacitance value [3:1 ] bal_cin balun input capacitance 0x0 rw 00 0 minimum capacitance value 111 maximum capacitance value address: 0x31, reset: 0x1101, name: mixer_ctl table 29 . bit descriptions for mixer_ctl bits bit name settings description reset access [12:10] mix_bias demod ulator (demod) bias value 0x4 rw [8:5] demod_rdac demod ulator linearizer rdac value 0x8 rw [3:0] demod_cdac demod ulator linearizer cdac value 0x1 rw rev. 0 | page 38 of 44
data sheet ADRF6820 address: 0x32, reset: 0x0900, name: mod_ctl0 table 30 . bit descriptions for mod_ctl0 bits bit name settings description reset access [11:10] polq quadrature polarity switch , q channel 0x2 rw 01 invert q channel polarity 10 normal polarity [9:8] poli quadra ture polarity switch, i channel 0x1 rw 01 normal polarity 10 invert i channel [7:4] qlo upp er side band nulling, q channel 0x0 rw [3:0] ilo upp er side band nulling, i channel 0x0 rw rev. 0 | page 39 of 44
ADRF6820 data sheet address: 0x33, reset: 0x0000, name: mod_ctl1 table 31 . bit descriptions for mod_ctl1 bits bit name settings description reset access [15:8] dcoffi baseband dc nulling, i channel 0x0 0 rw 00000000 0 a 00000001 +5 a 00000010 +10 a 00000011 +15 a 01111110 +94.5 a 01111111 +95.25 a 10000000 0 a 10000001 ? 5 a 10000010 ? 10 a 10000011 ? 15 a 11111110 ? 94.5 a 11111111 ? 95.25 a [7:0] dcoffq baseband dc nulling, q channel 0x0 0 rw 00000000 0 a 00000001 +5 a 00000010 +10 a 00000011 +15 a 01111110 +94.5 a 01111111 +95.25 a 10000000 0 a 10000001 ? 5 a 10000010 ? 10 a 10000011 ? 15 a 11111110 ? 94.5 a 11111111 ? 95.25 a rev. 0 | page 40 of 44
data sheet ADRF6820 address: 0x34, reset: 0x0b00, name: mod_ctl2 table 32 . bit descriptions for mod_ctl2 bits bit name settings description reset access [11:10] bb_bias baseband bi as select 0x2 rw 00 0 ma 01 4.5 ma 10 9 ma 11 13. 5 ma [9:8] bwsel b aseband gain and bandwidth select 0x3 rw 00 high g ain, h igh bandwidth ( refer to table 15) 01 high g ain, l ow bandwidth ( refer to table 15) 10 low g ain, h igh bandwidth ( refer to table 15) 11 low g ain, l ow bandwidth ( refer to table 15) rev. 0 | page 41 of 44
ADRF6820 data sheet address: 0x40, reset: 0x0010, name: pfd_ctl2 table 33 . bit descriptions for pfd_ctl2 bits bit name settings description reset access [6:5] abldly set antibacklash delay 0x0 rw 00 0 ns 01 0.5 ns 10 0.75 ns 11 0.9 ns [4:2] cpctrl set charge pump control 0x4 rw 000 both on 001 pump down 010 pump up 011 tristate 100 pfd [1:0] clkedge set pfd edge sensitivity 0x0 rw 00 div and ref down edge 01 div down edge, ref up edge 10 div up edge, ref down edge 11 div and ref up edge address: 0x42, reset: 0x000e, name: dith_ctl1 table 34 . bit descriptions for dith_ctl1 bits bit name settings description reset access 3 dith_en set dither enable 0x1 rw 0 disable 1 enable rev. 0 | page 42 of 44
data sheet ADRF6820 bits bit name settings description reset access [2:1] dith_mag set dither magnitude 0x3 rw 0 dith_val set dither value 0x0 rw address: 0x43, reset: 0x0001, name: dith_ctl2 table 35 . bit descriptions for dith_ctl2 bits bit name settings description reset access [15:0] dith_val set dither value 0x1 rw address: 0x45, reset: 0x0000, name: vco_ctl2 table 36 . bit descriptions for vco_ctl2 bits bit name settings description reset access [9:8] vtune_ctrl force internal vtune reference 0x0 rw address: 0x49, reset: 0x16bd , name: vco_ctl3 table 37 . bit descriptions for vco_ctl3 bits bit name settings description reset access [13:9] set_1 internal s ettings (r efer to the required pll/vco settings and register write sequence section ) 0xb rw [8:0] set_0 internal settings (refer to the required pll/vco settings and register write sequence section ) 0xbd rw rev. 0 | page 43 of 44
ADRF6820 data sheet out line dimensions figure 59 . 40 - lead lead frame chip scale package [ lfcsp _wq] 6 mm 6 mm body, very very thin quad (cp - 40 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADRF6820acpz -r7 ?40c t o +85c 40 - lead lead frame chip scale package [lfcsp_ wq ] cp -40 -7 ADRF6820 - evalz evaluation board 1 z = rohs compliant part. 06-04-2012- a 0.50 bsc bot t om view top view pin 1 indic a t or exposed pa d pin 1 indic a t or se a ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min * 4.70 4.60 sq 4.50 compliant to jedec standards mo-220- wjjd-5 with exception to exposed pad dimension. 40 1 11 10 20 21 30 31 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11990 - 0- 12/13(0) rev. 0 | page 44 of 44

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